View MC74HC573A_332786.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MC74HC573A Octal 3-State Noninverting Transparent Latch
High-Performance Silicon-Gate CMOS
The MC74HC573A is identical in pinout to the LS573. The devices are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched. The HC573A is identical in function to the HC373A but has the data inputs on the opposite side of the package from the outputs to facilitate PC board layout.
http://onsemi.com MARKING DIAGRAMS
20 PDIP-20 P SUFFIX CASE 738
1
MC74HC573AN AWLYYWW 1 20
20
* * * * * *
Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 218 FETs or 54.5 Equivalent Gates
20 1
SOIC WIDE-20 DW SUFFIX CASE 751D 1 TSSOP-20 DT SUFFIX CASE 948G
HC573A AWLYYWW 20 HC 573A ALYW 1
20 1
A WL YY WW
= Assembly Location = Wafer Lot = Year = Work Week
ORDERING INFORMATION
Device MC74HC573AN MC74HC573ADW MC74HC573ADWR2 MC74HC573ADT MC74HC573ADTR2 Package PDIP-20 SOIC-WIDE SOIC-WIDE TSSOP-20 TSSOP-20 Shipping 1440 / Box 38 / Rail 1000 / Reel 75 / Rail 2500 / Reel
(c) Semiconductor Components Industries, LLC, 1999
1
March, 2000 - Rev. 8
Publication Order Number: MC74HC573A/D
MC74HC573A
LOGIC DIAGRAM
D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 LATCH ENABLE OUTPUT ENABLE 2 3 4 5 6 7 8 9 11 1 PIN 20 = VCC PIN 10 = GND 19 18 17 16 15 14 13 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 NONINVERTING OUTPUTS
PIN ASSIGNMENT
OUTPUT ENABLE D0 D1 D2 D3 D4 D5 D6 D7 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 LATCH ENABLE
FUNCTION TABLE
Inputs Output Enable Latch Enable D H L X X Output Q H L No Change Z
L H L H L L H X X = Don't Care Z = High Impedance
II I I I IIIIIIIIIIIIIII IIIIIIIIIIIIIII II I IIIIIIIIIIIIIII II IIIIIIIIIIIIIII II IIIIIIIIIIIIIII II IIIIIIIIIIIIIII II IIIIIIIIIIIIIII II I II II I IIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIII II I IIIIIIIIIIIIIII
Design Criteria Value 54.5 1.5 5.0 Units ea. ns Internal Gate Count* Internal Gate Propagation Delay Internal Gate Power Dissipation Speed Power Product W pJ 0.0075 *Equivalent to a two-input NAND gate.
http://onsemi.com
2
MC74HC573A
IIIIIIIIIIIIIIIIIIIIII I II I I I I I IIIIIIIIIIII II III I I I I I II I I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIII I I I II IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I IIII I II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I
IIIIIIIIIIIIIIIIIIII II I IIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I II II I I I IIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIII II I II I I III II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II III II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS*
Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 35 75 750 500 450 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP SOIC Package TSSOP Package mW Tstg TL Storage Temperature - 65 to + 150 260
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
v
v
_C _C
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, TSSOP or SOIC Package)
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: -6.1 mW/C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Parameter
Min 2.0 0
Max 6.0
Unit V V
DC Supply Voltage (Referenced to GND)
Vin, Vout TA
DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1)
VCC
- 55 0 0 0
+ 125 1000 500 400
_C
ns
tr, tf
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol VIH
Parameter
Test Conditions
VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0
- 55 to 25_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9
v 85_C v 125_C
1.5 2.1 3.15 4.2 0.5 0.9 1.35 18 1.9 4.4 5.9 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 2.2 3.7 5.2
Unit V
Minimum High-Level Input Voltage
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
v v
VIL
Maximum Low-Level Input Voltage
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
V
VOH
Minimum High-Level Output Voltage
Vin = VIH or VIL |Iout| 20 A Vin = VIH or VIL
v
V
|Iout| 2.4mA |Iout| 6.0 mA |Iout| 7.8 mA
v v
2.48 3.98 5.48
2.34 3.84 5.34
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
http://onsemi.com
3
MC74HC573A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
IIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I II IIIII II II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II III I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I I I I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I II I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII III II II I I I I I IIIIIIIIIIIIIIIIIIIIII I II I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I III I I I I I II I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I
Guaranteed Limit Symbol VOL Parameter Test Conditions VCC V 2.0 4.5 6.0 3.0 4.5 6.0 6.0 6.0 - 55 to 25_C 0.1 0.1 0.1
v 85_C v 125_C
0.1 0.1 0.1 0.1 0.1 0.1 0.4 0.4 0.4 0.33 0.33 0.33
Unit V
Maximum Low-Level Output Voltage
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A Vin = VIH or VIL
v
|Iout| 2.4mA |Iout| 6.0 mA |Iout| 7.8 mA
v v
0.26 0.26 0.26
Iin
Maximum Input Leakage Current Maximum Three-State Leakage Current
Vin = VCC or GND
0.1
1.0
1.0 - 10
A A
IOZ
Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND IIoutI = 0 A
- 0.5
- 5.0
ICC
Maximum Quiescent Supply Current (per Package)
6.0
4.0
40
160
A
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol tPLH, tPHL
Parameter
VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0
- 55 to 25_C 150 100 30 26 160 105 32 27 150 100 30 26 150 100 30 26 60 27 12 10 10 15
v 85_C v 125_C
190 140 38 33 200 145 40 34 190 125 38 33 190 125 38 33 75 32 15 13 10 15 225 180 45 38 240 190 48 41 225 150 45 38 225 150 45 38 90 36 18 15 10 15
Unit ns
Maximum Propagation Delay, Input D to Q (Figures 1 and 5)
tPLH, tPHL
Maximum Propagation Delay, Latch Enable to Q (Figures 2 and 5)
ns
tPLZ, tPHZ
Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6)
ns
tPZL, tPZH
Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6)
ns
tTLH, tTHL
Maximum Output Transition Time, Any Output (Figures 1 and 5)
ns
Cin
Maximum Input Capacitance
pF pF
Cout
Maximum Three-State Output Capacitance (Output in High-Impedance State)
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V 23
CPD
Power Dissipation Capacitance (Per Enabled Output)*
pF
* Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
http://onsemi.com
4
II I I I I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIII I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIII I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I II I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I IIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII II I I I I I I I I IIIIIIIIIIIIII I I IIII III IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIIII III II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol tr, tf tsu tw th Maximum Input Rise and Fall Times Minimum Pulse Width, Latch Enable Minimum Hold Time, Latch Enable to Input D Minimum Setup Time, Input D to Latch Enable Parameter
http://onsemi.com
MC74HC573A
Fig.
1
2
4
4
5 VCC Volts 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 - 55 to 25_C Min 5.0 5.0 5.0 5.0 50 40 10 9.0 75 60 15 13 1000 800 500 400 Max Guaranteed Limit Min 5.0 5.0 5.0 5.0 95 80 19 16 65 50 13 11
v 85_C
1000 800 500 400 Max
Min
110 90 22 19 5.0 5.0 5.0 5.0 75 60 15 13
v 125_C
1000 800 500 400 Max
Unit
ns ns ns ns
MC74HC573A
SWITCHING WAVEFORMS
VCC tr INPUT D tPLH Q tTLH 90% 50% 10% tTHL Q 50% 90% 50% 10% tPHL tPLH tPHL tf VCC GND LATCH ENABLE 50% GND tw
Figure 1.
Figure 2.
OUTPUT ENABLE
3.0 V 50% GND tPZL tPLZ INPUT D HIGH IMPEDANCE 10% 90% VOL VOH HIGH IMPEDANCE LATCH ENABLE 50% GND tSU 50% GND th VCC VALID VCC
Q
50% tPZH tPHZ
Q
1.3 V
Figure 3.
Figure 4.
TEST POINT OUTPUT DEVICE UNDER TEST D0 2
EXPANDED LOGIC DIAGRAM
D Q LE D Q LE D Q LE D Q LE D Q LE D Q LE D Q LE D Q LE 11 19 Q0
CL*
D1
3
18
Q1
D2 *Includes all probe and jig capacitance
4
17
Q2
D3
5
16
Q3
Figure 5. Test Circuit
D4 6
15
Q4
TEST POINT OUTPUT DEVICE UNDER TEST 1 k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
D5
7
14
Q5
D6
8
13
Q6
CL*
D7
9
12
Q7
*Includes all probe and jig capacitance
LATCH ENABLE
Figure 6. Test Circuit
OUTPUT ENABLE
1
http://onsemi.com
6
MC74HC573A
PACKAGE DIMENSIONS
PDIP-20 N SUFFIX PLASTIC DIP PACKAGE CASE 738-03 ISSUE E
11
-A-
20
B
1 10
C
L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
-T-
SEATING PLANE
K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) TA
M
M
TB
M
DIM A B C D E F G J K L M N
SO-20 DW SUFFIX CASE 751D-05 ISSUE F
D A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1
10
h
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
DIM A A1 B C D E e H h L
L
18X
e
A1
q
T
C
http://onsemi.com
7
MC74HC573A
PACKAGE DIMENSIONS
TSSOP-20 DT SUFFIX CASE 948E-02 ISSUE A
M
20X
K REF TU
0.15 (0.006) T U
S
0.10 (0.004)
S
V
S
2X
L/2
20
11
L
PIN 1 IDENT 1 10
B -U-
J J1
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com Fax Response Line: 303-675-2167 or 800-344-3810 Toll Free USA/Canada N. American Technical Support: 800-282-9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor - European Support German Phone: (+1) 303-308-7140 (M-F 1:00pm to 5:00pm Munich Time) Email: ONlit-german@hibbertco.com French Phone: (+1) 303-308-7141 (M-F 1:00pm to 5:00pm Toulouse Time) Email: ONlit-french@hibbertco.com English Phone: (+1) 303-308-7142 (M-F 12:00pm to 5:00pm UK Time) Email: ONlit@hibbertco.com EUROPEAN TOLL-FREE ACCESS*: 00-800-4422-3781 *Available from Germany, France, Italy, England, Ireland CENTRAL/SOUTH AMERICA: Spanish Phone: 303-308-7143 (Mon-Fri 8:00am to 5:00pm MST) Email: ONlit-spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor - Asia Support Phone: 303-675-2121 (Tue-Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: 001-800-4422-3781 Email: ONlit-asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-8549 Phone: 81-3-5740-2745 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local Sales Representative.
http://onsemi.com
8
IIII IIII IIII
SECTION N-N 0.25 (0.010) M DETAIL E DETAIL E
K K1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
DIM A B C D F G H J J1 K K1 L M
MC74HC573A/D

▲Up To Search▲

Price & Availability of MC74HC573A

	To Download MC74HC573A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .